First of all - the benefit of ABV is to catch errors early. Not sure why you would want to wait till end of sim to report the error. But I believe you have a reason, but do revisit that at your end.
Moving to the coding front, do you want PSL or SVA? Assuming SVA, you will anyway be using “bind” to bind the SVA module/interface to the VHDL entity. In that case, best is to add the “final block” into the SVA module itself. So Ben’s code snippet should work even in a Mixed language scenario.
VHDL does have an equivalent to $finish, env.finish; - strongly recommend you use that than the “severity” route (old approach).
Good Luck
Srini
www.verifworks.com