How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation?

SystemVerilog
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3

Thanks!

I meant I want to get a notification if the signal was never HIGH during the whole simulation.

As far as I understand, the assert property(@(posedge clk)(not(x))or(not($rose(x)))) issues a notification when the signal is HIGH/raised on any posedge clk;

Actually I need an assertion, which will issue a notification in the END of SIMULATION if the assertion’s condition was not fulfilled.

Thank you!