How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation?

SystemVerilog
, ,
19

In reply to prashantk:

But the thing is final keyword is not compliant with 1800-2009 LRM so I used the later code.One more thing is I want my assertion to starts only after certain time stamp … Is there any way to do that ?.

SO your time stamp is $rose(signal[a]) && $rose(signal[b])
If that is your timestamp you can use something like.


initial begin :b1
  wait($rose(signal[a]) && $rose(signal[b])); // waiting for the timestamp
  // that timestamp can also be generation from an assertion action block or from a 
  // a function call from within a concurrent assertion in a sequence_match_item 
  // See below
  //@(posedge clk); // another wait if that s what you want
  forever assert #0 (sig) else $display("error message here"); // unclocked, constantly checked
                                 //error message in the Reactive region  
end : b1 
// Other option
  bit timestamp; 
  function void set_timestamp(int a); 
    timestamp=a; 
  endfunction : invert_auto  
  ap_gen_timestamp1:  cover property(@(posedge clk) 
         ($rose(signal[a]) && $rose(signal[b]), set_timestamp(1'b1) ) ); 
  // Another option, you define that time region 
  //  ap_gen_timestamp1:  cover property(@(posedge clk) 
         $rose(signal[a]) && $rose(signal[b]) ##1 (1'b1, set_timestamp(1'b1)) );  
initial begin :b1
  wait (timestamp); 
  forever ...

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us