How to check if a signal is in a clock domain

SystemVerilog
2

In reply to abasili:

This assumes all the external IPs have NO delays, even a #1. Also this code needs to be in a timescale so that $realtime always returns an integer; otherwise the modulo operator will not work.

You can use
always @(signal iff (!$isunknown(signal) ) to get rid of X transitions.

A much better approach is using a formal CDC checking tool. With little or no stimulus at all, a CDC can trace all the domain crossings exhaustively.