How to change the value of distributed weighted constrained random generation

SystemVerilog
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2

In reply to rupeshblr:

You can change 5, 8, and 12 to be parameters instead of literals. But a much easier solution is making them class variables so there are no class type compatibility issues.

class packet;
  rand bit [3:0] addr;
  int W1=5, W2=8, W3=12;
  constraint addr_range { addr dist { 2 := W1, 7 := W2, 10 := W3 }; }
endclass
class skew_packet extends packet;
function new;
  W1=12,W2=5,W3=8;
endfunction
endclass