How to bind an interface with system verilog module?

Hi Srini/Chris?

I have seen both kinds of interface definition, the one you have mentioned and the one I have showcased.

The one you have showcased is the typical interface that UVM cookbook and most UVMers recommend.

But the one i have shown comes with an added advantage, it can be used to bind with modules and sub-modules easily.

@Chris,
The code snippet that you have shown does not look syntactically correct(though i have not compiled it).