In reply to megamind:
SystemVerilog is a collection of technologies from different languages and there can be more than one way to accomplish the same thing. This holds true for most programming languages— they all borrow from each other.
As far as non-blocking assignments versus clocking blocks, you should pick one methodology and not mix them, at least within the same driver/interface pair.
You are correct in observing that races can be eliminated if both DUT and testbench use non-blocking assignments correctly. Clocking blocks are more tolerant with designs that have not used non-blocking assignments or gate-level descriptions with inaccurate timing. However, those cases will be more prone to race conditions within the DUT.