How to assign and create associative array with multiple keys

SystemVerilog
,
3

In reply to dave_59:

i was trying to make data as associative array since i want to find the elements in data array using one of the keys or even the entire combination of the keys.
like
data_out = data[key’{4’b1,12’habc,32’hf}].exists()?data[key’{4’b1,12’habc,32’hf}]:0;

i am trying to achieve something like this:

typedef struct {bit [3:0] id; bit[11:0] addr; bit[31:0] byte_en;} key;
bit[255:0] data[key];
bit[255:0] data_out; 
module top;
  initial 
    begin 
      data[key'{4'b1,12'hdef,32'hf}] = {256'ha0a05a5a};
      data[key'{4'b1,12'habc,32'hf}] = {256'hb0b05b5b};
      data_out = data[key'{4'b1,12'habc,32'hf}].exists()?data[key'{4'b1,12'habc,32'hf}]:0;
      $display ("data_out=%0d",data_out);
    end
endmodule