How to assert property in for loop for i nos of times and j number of times to reduce writing assert for all hierarchy

SystemVerilog
1

Hi Ben,

I have following question to how to execute a property making it generic and calling it n number of times in for loop so that we can cover for all registers in different hierrachy.

`define PHY_A_REG_(num) top.a.b_``num``.c.r_reg_a
`define PHY_B_REG_(num)  top.a.b_``num``.c.r_reg_b
`define PHY_C_REG_(num)  top.a.b_``num``.c.r_reg_c
`define PHY_D_REG_(num)  top.a.b_``num``.c.r_reg_d

This four registers of PHY type has 11 variations so num does it for them.

`define IOB_A_REG_(num) top.a.b.c.d.e.f_pair``num``_regs.r_reg_a
`define IOB_B_REG_(num) top.a.b.c.d.e.f_pair``num``_regs.r_reg_b
`define IOB_C_REG_(num) top.a.b.c.d.e.f_pair``num``_regs.r_reg_c
`define IOB_D_REG_(num) top.a.b.c.d.e.f_pair``num``_regs.r_reg_d

property kNpi_register_check_all(clk_npi, a,b,c,d);
   @(posedge clk)
   $fell(a) |-> ##[16245:16246] (b==0) && (c==1) && (d==0);
   endproperty



  assert_npi_register_nibble0_checking_all : assert property (kNpi_register_check_all(top.b.c.clk,`PHY_A_REG_(1),`PHY_B_REG_(1),`PHY_C_REG_(1),`PHY_D_REG_(1)))
  else `ASSERT_ERROR ("Assertion  check pattern error","ALERT: global signalsa not follwing the pattern")

 assert_npi_register_nibble0_checking_all : assert property (kNpi_register_check_all(top.b.c.clk,`PHY_A_REG_(10),`PHY_B_REG_(10),`PHY_C_REG_(10),`PHY_D_REG_(10)))
  else `ASSERT_ERROR ("Assertion  check pattern error","ALERT: global signalsa not follwing the pattern")

 assert_npi_register_nibbleiob1_checking_all : assert property (kNpi_register_check_all(top.b.c.clk,`IOB_A_REG_(1),`IOB_B_REG_(1),`IOB_C_REG_(1),`IOB_D_REG_(1)))

  else `ASSERT_ERROR ("Assertion  check pattern error","ALERT: global signalsa not follwing the pattern")

hierarachy 1:(PHY) same four reg have 11 variations:44
hireachy 2:(IOB) has 3 variations with same reg name

can we assert the property in for loop as we need to call each unique one 47 times can we add for loop to make it unique

If yes then how

2 
begin
        
  assert_npi_register_nibble0_checking_all_(i): assert property (kNpi_register_check_all(mc_tb_top.hsm_xpio_u.xp5io_bank_inst.npi_clk,`PCSR_LOCKSTATE_REG_(i),`PCSR_TRISTATE_REG_(i),`PCSR_COMPLETE_REG_(i),`PCSR_GATEREG_REG_(i)));
  else `ASSERT_ERROR ("Assertiion  check pattern error %0d",i); //ALERT: global signalsa not following the pattern
end

case2:

for(genvar i=0;i<11;i++)
begin
        
  assert_npi_register_nibble0_checking_all_[i]: assert property (kNpi_register_check_all(mc_tb_top.hsm_xpio_u.xp5io_bank_inst.npi_clk,`PCSR_LOCKSTATE_REG_(i),`PCSR_TRISTATE_REG_(i),`PCSR_COMPLETE_REG_(i),`PCSR_GATEREG_REG_(i)));
  else `ASSERT_ERROR ("Assertiion  check pattern error %0d",i); //ALERT: global signalsa not follwing the pattern
end

case 3:i

for(genvar i=0;i<11;i++)
begin
        
  assert_npi_register_nibble0_checking_all_``i``: assert property (kNpi_register_check_all(mc_tb_top.hsm_xpio_u.xp5io_bank_inst.npi_clk,`PCSR_LOCKSTATE_REG_(i),`PCSR_TRISTATE_REG_(i),`PCSR_COMPLETE_REG_(i),`PCSR_GATEREG_REG_(i)));
  else `ASSERT_ERROR ("Assertiion  check pattern error %0d",i); //ALERT: global signalsa not follwing the pattern
end

for all i see syntax error

3

Please format your code blocks making your code easier to read. I have done that for you.