module par2ser;
bit[7:0] data;
bit clk, sync, serial;
property p_data_msb2lsb; // updated
bit[7:0] v_data, v_collected;
bit[2:0] i;
@(posedge clk)(sync, v_data=data, i=0) |=> // serial output is from lsb to msb
(1, v_collected[i]=serial, i=i+1'b1)[*8] ##1 v_collected==v_data;
endproperty
property p_data_lsb2msb; // updated
bit[7:0] v_data, v_collected;
bit[2:0] i;
@(posedge clk)(sync, v_data=data, i=7) |=> // serial output is from msb to lsb
(1, v_collected[i]=serial, i=i-1'b1)[*8] ##1 v_collected==v_data;
endproperty
ap_data_msb2lsb: assert property(p_data_msb2lsb);
a_data_lsb2msb: assert property(_data_lsb2msb);
endmodule
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books