How to access configurations in side the interface for Assertions

UVM
1

Hi,
I have assertions that are written in side the interface and there are some configurations in the base test i want to use in the assertions so how i access these configurations inside the interface?

Thanks.

2

Could you give us some more information about the data you are using in the interface? Is it parameter or what is it?

3

Hello,
No there is no parameters i want to access some configuration registers from the base test and use it in assertions

Thanks.

4

I can think of 2 choices:

  1. Use a config class and set/get using uvm_config_db::set(null…) (Use global namespace or create a dummy scope)
  2. Use virtual interface to set inside test, access it from within your SVA module

HTH
Srini

5

Hello,

I tried getting this using config_db but getting compilation error in the interface that the instance of the register config is unknown type.

as you can see in the screenshot i am importing the spi_uvc_pkg in top module.

image
image942×329 17.7 KB

in the base test i am setting the register configuration
/** Set the register configuration*/
uvm_config_db#(spi_uvc_reg_cfg)::set(null,“*”,“spi_reg_cfg_h”,spi_reg_cfg_h);

and in the assertions which is an interface which i am binding to top module in that i am getting the reg config like this

/** SPI reg config instance*/
spi_uvc_reg_cfg spi_reg_cfg_h;

/** Retriving the reg configuration classs */
if(!uvm_config_db#(spi_uvc_reg_cfg)::get(null,"","spi_reg_cfg_h",spi_reg_cfg_h))
  `uvm_fatal(get_full_name(),"not able to get reg config");
6

I don’t see any import, try importing that PKG inside interface. Maybe you are mixing include and import?