In reply to mlsxdx:
The difference is that SystemVerilog’s force construct searches for pathnames at the compilation time and symbolically binds the path to the assignment statement, the same as it does for any kind of hierarchical reference in any kind of statement.
The UVM’s uvm_hdl_force() method uses the C VPI interface to search for signal using a string pathname at runtime. Once it finds the signal via a string loop-up, it uses another C VPI routine that applies a force. In order to lookup a signal using a string pathname, certain optimizations need to be turned off that keeps the signal visible, and the string names have to be stored as well. There may be tool specific options to make this work, and this forum is not for tool specific help.