The recommendation here is to write code that is synchronous to only one clock edge, do not use mixtures of different signal edges and wait statements. Only use
@(posedge sigs.ecu_clk); or @(posedge sigs.ecu_clk iff (signal == value));
The signals that you sample must be written with non-blocking assignments, just like RTL designers would do to avoid race conditions, or you can use clocking blocks to sample the signals. Once you start using clocking blocks, you should only use the clocking block event to synchronize your code.