How do I disable pre_randomize function?

SystemVerilog
1

How do I disable pre_randomize function that gets called by default for a particular instance of class when I do class_h.randomize()? other class handles can call randomize and then call pre_randomize function by default and execute but not for this specific handle. is extending and overriding pre_randomize the only possible solution? other solution would be: std::randomize(c1_h.r1) with {c1_h.r1 == 3;};

module m1;

  class c1;
  rand int r1;
  int r2;
  
  constraint c1_c{(r2!=0) -> r1 == r2;}
  
  function void pre_randomize();
    r2 = 'd2;
  endfunction
  
  endclass
  
  initial begin
    c1 c1_h = new();
    c1 c11_h = new();
    c1_h.randomize();//how to disable pre_randomize to this handle only
    c11_h.randomize();
    $display("r1 is %0d", c1_h.r1);
    $display("r1 is %0d", c11_h.r1);
  end
  
endmodule
2

You could have a separate property for this within class c1

 class c1;
  bit skip_pre_rand ;
  .....
  function void pre_randomize();
      if( !skip_pre_rand) begin
          r2 = 'd2; 
      end
  endfunction
endclass

 c1 c1_h , c11_h;

   initial begin
     c1_h = new();
   c11_h = new();
  c11_h.skip_pre_rand = 1;
    c1_h.randomize();   // Should check the Success / failure of randomize()
    c11_h.randomize(); // Should check the Success / failure of randomize()
    $display("r1 is %0d", c1_h.r1);
    $display("r1 is %0d", c11_h.r1);
  end
  
endmodule
1 Like
3

Thanks!