How do I disable base class constraints in a transaction extension?

SystemVerilog
2

In reply to bmorris:
You actually now have 4 different choices for doing this.

  1. Override with an empty constraint, and add new constraint. This runs the risk of having a typo and winding up with both constraints active.
  2. Override with a replacement constraint. This shows your intent with the most clarity.
  3. Disable the base constraint using constraint_mode in the extended constructor. This allows you to turn it back on later if needed in the sequence, or an extended sequence.
  4. Use a soft constraint. This allows you to add new constraints, and only removes the existing soft constraint if it conflicts. I find this either works great for some situations, and doesn’t work for other situations.