I am writing a TB for Async FIFO and i have a problem where i need to control the winc and readinc based on wclk and rclk respectively. I have provided my write seq and write driver. I want to contstraint the winc such that it is a clock divide by 2 and then i assign it to wdata.Similarly on the read side. Can any one help? Really appreciate it.
Ex :
for (int i=0; i<32; i++) begin
@(posedge BUS.wclk iff !BUS.wfull);
winc = (i%2 == 0)? 1’b1 : 1’b0;
if (winc) begin
BUS.wdata <= req.wdata ;
class wr_seq extends uvm_sequence #(bus_seq_item);
`uvm_object_utils(wr_seq)
bus_seq_item req;
bus_agent_config m_cfg;
bit writeinc;
// virtual bus_if BUS;
rand int limit = 40; // Controls the number of iterations
function new(string name = "wr_seq");
super.new(name);
endfunction
task body;
req = bus_seq_item::type_id::create("req");
if(!uvm_config_db #(bus_agent_config)::get(null, get_full_name(), "config", m_cfg)) begin
`uvm_error("body", "unable to access agent configuration object")
end
repeat (limit)
begin
start_item(req);
assert(req.randomize with {winc ==1;rinc==0;})
finish_item(req);
// The req handle points to the object that the driver has updated with response data
`uvm_info("seq_body", req.convert2string(), UVM_LOW);
end
endtask: body
endclass: wr_seq
class wr_driver extends uvm_driver #(bus_seq_item);
`uvm_component_utils(wr_driver)
bus_seq_item req;
int i;
bit localwrinc;
virtual bus_if BUS;
function new(string name = "bus_driver", uvm_component parent = null);
super.new(name, parent);
endfunction
task run_phase(uvm_phase phase);
// Default
BUS.wdata <= 0;
BUS.winc <= 0;
// Wait for reset to end
@(posedge BUS.wrst_n);
forever
begin
seq_item_port.get_next_item(req);
@ (posedge BUS.wclk) ;
BUS.winc <= req.winc;
BUS.wdata <= req.wdata;
seq_item_port.item_done();
// end
end
endtask: run_phase
endclass: wr_driver[\systemverilog]