How do I connect my analysis_export in my scoreboard to the "trans_ap" analysis_port in the AXI QVIP agent?

UVM
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1

From these 3 lines one can probably infer details of our QVIP AXI slave.
umc0_xs22_c = new(“umc0_xs22”, AXI_SLAVE, s_64_8);
amba_interfaces.ports.push_back(umc0_xs22_c);
uvm_config_db #(s_64_8_axi_t)::set( null, “uvm_test_top” , “umc0_xs22” , `get_interface(umc0_xs22) )

Here is the run error message from mti.log.

** Error: (vsim-3978) /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env.svh(269): Illegal assignment to class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mvc_pkg::mvc_sequence_item_base, class work.mvc_pkg::mvc_sequence_item_base)) from class mtiUvm.uvm_pkg::uvm_analysis_export #(class work.mgc_axi_v1_0_pkg::axi_master_rw_transaction #(32, 64, 64, 8))

Time: 0 fs Iteration: 0 Region: /env_pkg File: /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env_pkg.sv

** Error: (vsim-8754) /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env.svh(269): Actual input arg. of type ‘class mtiUvm.uvm_pkg::uvm_analysis_export #(class work.mgc_axi_v1_0_pkg::axi_master_rw_transaction #(32, 64, 64, 8))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mvc_pkg::mvc_sequence_item_base, class work.mvc_pkg::mvc_sequence_item_base))’.

Here is the source which generates the error:

Here is env.svh(269).
Line 269: agents[“umc0_xs22”].ap[“trans_ap”].connect( sdmgr_scoreboard.ddr_trans_export );

class sdmgr_scoreboard_c extends uvm_scoreboard;
`uvm_component_utils(sdmgr_scoreboard_c);

//`define s_64_8 32,64,64,8 //FYI

uvm_analysis_export #(axi_master_rw_transaction #(s_64_8) ) ddr_trans_export; axi_master_rw_transaction #(s_64_8) ddr_pkt;

endclass

Here is another attempt which didn’t work!
//in build phase
void’(main_config.m_configs[“umc0_xs22”].set_monitor_item(“chris_ap” , s_64_8_axi_rw_trans_t::type_id::get()));
//in connect phase
agents[“umc0_xs22”].ap[“chris_ap”].connect( sdmgr_scoreboard.ddr_trans_export ); //env.svh(333)

//run time error

** Error: (vsim-3978) /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env.svh(333): Illegal assignment to class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mvc_pkg::mvc_sequence_item_base, class work.mvc_pkg::mvc_sequence_item_base)) from class mtiUvm.uvm_pkg::uvm_analysis_export #(class work.mgc_axi_v1_0_pkg::axi_master_rw_transaction #(32, 64, 64, 8))

Time: 0 fs Iteration: 0 Region: /env_pkg File: /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env_pkg.sv

** Error: (vsim-8754) /proj/eldorah1/wa/cturner/design/sata_dmgr_subsys/sim/env/env.svh(333): Actual input arg. of type ‘class mtiUvm.uvm_pkg::uvm_analysis_export #(class work.mgc_axi_v1_0_pkg::axi_master_rw_transaction #(32, 64, 64, 8))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_tlm_if_base #(class work.mvc_pkg::mvc_sequence_item_base, class work.mvc_pkg::mvc_sequence_item_base))’.

2

You should contact Mentor directly for product specific help.

3

In reply to cturner:

Hi,

Are you able to resolve these errors?
Even I am getting same errors.

Thank You.

4

In reply to ma2845ghty:

Yes, we have solved this problem!
The simple answer is that mvc ports are specialized as mvc_sequence_item_base so all connecting ports must be specialized the same.

The connection to trans_ap in our environment:
agents[“umc0_xs22”].ap[“trans_ap”].connect( sdmgr_scoreboard.ddr_trans_export );

The key portions of our scoreboard:
uvm_analysis_export #(mvc_sequence_item_base ) ddr_trans_export;
uvm_tlm_analysis_fifo #(mvc_sequence_item_base ) ddr_trans_fifo;
axi_master_rw_transaction #(32,64,64,88) ddr_pkt;
mvc_sequence_item_base generic_qvip_pkt;

forever begin: GET_DDR_TRANS
ddr_trans_fifo.get(generic_qvip_pkt);
if (!$cast(ddr_pkt,generic_qvip_pkt)) begin
uvm_error(report_id,$psprintf("cast failed")); end uvm_info(report_id,“DDR_TRANS”,UVM_LOW);
end: GET_DDR_TRANS

5

The simple answer is that mvc ports are specialized as mvc_sequence_item_base so all connecting ports must be specialized the same.