How could I co-simulate a baseline and modified DUT?

I have a baseline DUT that works pretty well and I want to add some new functionality to it. My plan is to set up a verification environment that instantiates both the baseline module and the modified one. Then I run the same inputs to both and compare the common outputs to verify that they are still identical.

The problem I have is that to make my changes, I have to modify files common to both versions. I can easily copy the baseline code to another folder, but I can’t figure out how to get Questa to run two modules that have the same module name but different code side-by-side in the same simulation.

Can this be done?


A Verilog configuration can help you here. (config/endconfig)

In reply to dave_59:

Hi Dave/VA,

Could you please elaborate on the usages of configuration?
It is present in the legacy code of current place.
Trying to understand its purpose.


In reply to Michael54:

SystemVerilog created configurations (actually appropriated from VHDL) primarily to address the problem the original poster mentions—you have two module definitions with the same name and you need both of them in the same design/simulation.

Configurations allow you to compile modules into different logical libraries and then based on an instance specific scope, select which library you want the module definition to come from. In this case it’s two different revisions of the same module, but sometimes it’s two different abstraction levels of the same module. Another use case is when you are combining IP from different project that happen to use the same module name at lower levels of each design (e.g. both have a ‘controller’ module, but they are completely different definitions.

Even though this feature was added to Verilog-2001, there were already tool specific command line options to dealt with this. Adoption is very slow.