How can i use conditional bins in system verilog coverage?

SystemVerilog
1

Hi,

I want to restrict the bins for the variable a, if variable b is equal to 2.I have used this code i am not getting any output?

module tb;
 
  reg [3:0] a;
  reg [1:0] b;
 integer i = 0;
  
  covergroup c;
    option.per_instance = 1;  
    coverpoint a{
      bins zero[]= {0,1} with(b == 2);
      bins one[]= {4,5,6};
    }
  endgroup 
  
 
  c ci;
 
  initial begin
    ci = new();
  
    for (i = 0; i <10; i++) begin
      a = $urandom();
      b = $urandom();
      ci.sample();
      #10;
    end
    
    
  end
  
  initial begin
    $dumpfile("dump.vcd"); 
    $dumpvars;
    #500;
    $finish();
  end
  
endmodule



####run.do file
vsim +access+r;
run -all;
acdb save;
acdb report -db  fcover.acdb -txt -o cov.txt -verbose  
exec cat cov.txt;
exit

Can someone help me?

2

There are two kinds of “conditional” bins,

The with() clause conditionally. creates a bin when the covergroup gets constructed. In your example, b is unknown, so there are no zero bins. You cannot change the number bins once constructed.

The iff () conditionally samples. the bin when the expression is true. What are you looking to do?

3

Hi Dave,

I should create the bin zero, only when b ==2. so, should i use iff or with clause?

4

Use the with clause and set b before constructing the covergroup.

Note that some tools produce a warning if you try declaring bins with an empty set of bins.

A better practice is splitting your bins into separate coverpoints, then setting the option weight to 0.

 covergroup c;
    option.per_instance = 1;  
    zero: coverpoint a{
      bins zero[]= {0,1};
    }
    one: coverpoint a{
      bins one[]= {4,5,6};
    }
  endgroup 
  c ci;
  initial begin
    ci = new();
    b = $urandom();
    if (b != 2)
      c::zero::type_option.weight = 0;
    ...
end