How can I quantify the coverage in scenario verification?

I use some test patterns in System level verification.
The main purpose is to verify functionality of BUS and DDR.
But, I’m not a BUS designer but DV engineer doing prototyping SoCs.
I mainly check if the transaction is working well between CPU, BUS and DDR.

Q1. After I change the fixed test pattern to random test patten, What metrices can explain the increase in coverage?

In reply to Lily_y:

This seems like a very open-ended interview question. The idea behind constrained random verification is generating many test patterns quicker than you could ever write fixed patterns. More patterns, better coverage.