How can i increase the simulation time in UVM

UVM
1

Hi,

I have integrated a UVM testbench with the VHDL design. But the issue occurs due to the end of the simulation at 150 ps whereas i have given in the top file.

module tb_top

initial
begin
#10000 $finish;
end
endmodule

So, the simulation should end at 10000ps.

2

In reply to shankar_logic:

You should read the section on the Verification Academy on how UVM determines the end of a test.

If your UVM test ends, your simulation will also end.

3

In reply to shankar_logic:

What #10000 means depends on the time resolution, i.e. it does not mean 150 ps in any case.
But UVM provides you with the objection mechanism which stops the simulation after finishing the corresponding test. If you do not implement the objections your simulation comes at time 0 to the end.
Never use an absolut time with $finish/$stop to finish the simulation.

4

Thanks it worked for my testbench