In reply to hal9e3:
OK, solved this but had to go outside SVA to do it:
bit start_asserts;
always @(posedge clk) begin
if (rst !== 1) begin
#1 start_asserts <= 0;
end
else if ((d == SYNC_DATA) & !available) begin
#1 start_asserts <= 1;
end
else begin
#1 start_asserts <= start_asserts;;
end
end
property data_parity_prop (clk, rst, d, available, parity, start_asserts);
@(posedge clk) disable iff (rst !== 1)
start_asserts |-> (^d ^ available ^ parity);
endproperty
Not pretty or elegant but it works.