How Can I Hold Off an Assertion Until Sync is Established Using a Local Variable?

SystemVerilog
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6

In reply to hal9e3:

Did you use this?
($rose(d == SYNC_DATA), flag = 1) or flag |-> ^d ^ available ^ parity;
This states that a new d==SYNC_DATA will set the flag.
To get A part of the property fired one and ONLY ONCE, you could do this

property data_parity_prop (clk, rst, d, available, parity);
  bit flag = 0;
  bit done= 0;
  @(posedge clk) disable iff (rst !== 1)
((d == SYNC_DATA && !done), flag = 1, done=1) or flag |-> ^d ^ available ^ parity;
endproperty
// or more simply with one variable 
property data_parity_prop (clk, rst, d, available, parity);
  bit flag = 0;
  @(posedge clk) disable iff (rst !== 1)
((d == SYNC_DATA && !flag), flag = 1) or flag |-> ^d ^ available ^ parity;