You needed the property “or” operator.
property data_parity_prop (clk, rst, d, available, parity);
bit flag = 0;
@(posedge clk) disable iff (rst !== 1)
((d == SYNC_DATA), flag = 1) or flag |-> ^d ^ available ^ parity;
endproperty
// Could also use
property data_parity_prop (clk, rst, d, available, parity);
bit flag = 0;
@(posedge clk) disable iff (rst !== 1)
($rose(d == SYNC_DATA), flag = 1) or flag |-> ^d ^ available ^ parity;
endproperty
// Suggest you also use the default disable iff
property_expr ::=
sequence_expr
| strong ( sequence_expr )
| weak ( sequence_expr )
| ( property_expr )
| not property_expr
| property_expr or property_expr // <-----------
| property_expr and property_expr
| sequence_expr |-> property_expr
| sequence_expr |=> property_expr
…
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115