In reply to VerificationLearn:
It would be very helpful if you post a complete, self-contained example which can be run. This ensures that others see exactly what the issue is.
Are you trying to read a string name of a register and then assign a value to that register? If so, you can not do that in SystemVerilog. You would have to compare the string to a known value and then assign the register appropriately.
If this is not what you want to accomplish, you will have to explain your issue more clearly.