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I’m trying to understand about down casting and up casting.
For example
class base;
int a = 5;
endclass
class extend extends base;
int a = 1;
int b = 8;
endclass
module test;
initial begin
base m_base;
extend m_extend;
//Down Cast
m_extend = new();
m_base = m_extend;
$display(m_base.a); //5 not 1.
$display(m_base.b); //Error
end
endmodule
As I know, Example above, m_base copy m_extend’s property But Handle does not change. So We have to use m_base handle not m_extend.
How do I get accessibility of subclass variables in Down Casting in Systemverilog?
In reply to UVM_LOVE:
m_base = m_extend; is an example of upcasting. In any cast, you are not copying class properties or objects, just the class handle.
You have asked very similar questions before. You should look at my short course on SystemVerilog OOP.
Thank for Reply.
I found that Down casting not allow but if between them have same type, we can use down casting right?
we can down casting if they have pointed same object.
For example)
Base B1 B2
EXTEND E1 E2
E1 = new();
B1 = E1; // this is upcasting and is always legal.
B2 = E1; // this is upcasting and is always legal.
E2 = new();
B1 = E2; // this is upcasting and is always legal.
B2 = E2; // this is upcasting and is always legal.
//////////////////////////////////////////////////
E1 = new();
B2 = E1;
$cast(E2, B2) // this is downcast . Base class handle can not be copied to Extended class handle and it's compilation error. But $case operation firstly check type. So if they object type(extend or base) is pointing the same object then will pass downcasting.
Right?