In reply to gopal_susarla:
Yes, the testbench is normally configured only in the build phase.
With respect to multiple testbench configurations, there are several considerations which you need to take into account when you are designing your environment:
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Is your DUT parameterized? If so, you will need to have these parameters set at the top testbench level. These parameters will then need to be identical in your UVM environment.
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Does the bit width really affect your stimulus generation? Many times you can use integers for stimulus and only use the required number of bits. This keeps you from having to use parameters for data elements.
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Does the port selected really affect the DUT? What happens when you use both ports at the same time? Your tests could be designed to send stimulus to both ports and predict the DUT response appropriately.
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If your DUT is not parameterized but only configurable, then you can use a randomized configuration. I would recommend randomizing the configuration only once at the test level, but you could use a loop to create different configurations. Note that these configurations aren’t needed in the build phase, but only control how the DUT is configured via registers.