How are race conditions betwen DUT and UVM are prevented?

UVM
2

In reply to Stechbeitel:

Finally there is no absolute need to use a clocking block or a program to prevent your testbench/DUT system from race conditions. I have never used in any of my UVM tesstbenches both of them. Most designs are working on 1 edge. I’m driving the design on the rising edge (driver) and observing on the falling edge (monitor). If you have a VHDL DUT, then you do not face the race conditions.