hello everyone! in my testbench i have to make a random signal “[31:0] distortion”. it must contain one (or, in other case, two) hot bit(s) (hot bit is “1”, all others are “0”). So i have a problem with writing a constraint: i really don’t want to write all possible combinations of these bits (if t…

Rather than constrain distortion[31:0] to be one-hot or two-hot, how about doing the following: randc bit [5:0] one_hot_bit; randc bit [5:0] two_hot_bit; constraint c_two_hot_bit { two_hot_bit != one_hot_bit; } function bit [31:0] calc_distortion(bit [5:0] ohb); bit [31:0] d; d = 32'd1 << ohb;…

Use $countones system-function rand bit [31:0] vec_1; constraint cst_max_2_hot_bits { $countones(vec_1) inside {1,2}; } // cst_max_2_hot_bits HTH, Ajeetha, CVC Verification Course Blog | VeriLog Courses | CVC Read our verification course blog to find out more about what C…

In reply to ajeetha : I have one more solution for the same. In this, randomization does not repeat until all the possible states. class one_hot; rand bit[0:31] state; randc bit[0:4] one_hot_bit; constraint one_hot_state { foreach (state[i]) if(i == one_hot_bit) state[31-i]==1; else state[31-…

In reply to vybhava : I use ies12.10.008, ies12.20.006 and VCS2012.09beta for this method of constraint. But it doesn’t work. In this version of tools, we can use $countones(vec_1) to calculate the number of bit 1, but not use this system function in constraint. Please tell me which version and tool…

In reply to gaurson : I used Questa 10.2. Is there a detailed error message from other tools with pointers to LRM? Ajeetha, CVC Verification Course Blog | VeriLog Courses | CVC Read our verification course blog to find out more about what CVC can offer, if you are looking for online co…

In reply to ajeetha : A quick follow-up. Found 2 relevant mantis items: http://www.eda.org/svdb/view.php?id=2476 http://www.eda.org/svdb/view.php?id=3054 Looks like Questa has implemented this feature ahead of others. Check with your vendor on their plans for this handy feature. Ajeetha, CVC …

In reply to ajeetha : Hi Ajeetha, I like your solution, even if it only runs on Questa at the moment! However, using an inside constraint will give a value with 2 bits set to 1, most of the time (presumably because the constraint solver has to pick a value for vec_1 before calling $countones and t…

In reply to dlong : Dave, You are correct that without the dist constraint, the number of solutions with 2 bits set ( 496 ) is much greater than the number of solutions with 1 bit set ( 32 ). But these built-in iterative constraints are expanded out as an equation like ( int'(vec_1[31]) + int'(vec_1[…

In reply to dave_59 : In ies and VCS, the error message is that a system function or task call can not be used within a constrain expression. Maybe Questa have the feature and others dont.

Hi Dave, Thanks for the explanation - very interesting! Is the mechanism you describe a “feature” of the way in which system functions are implemented in Questa rather than something I could find in the standard? The text in section 18.5.12 says “Functions shall be called before constraints are s…

"hot bit" randomization

SystemVerilog

Ajeetha_Kumari_CVC April 21, 2013, 2:30am 6

In reply to gaurson:

I used Questa 10.2. Is there a detailed error message from other tools with pointers to LRM?

Ajeetha, CVC