"hot bit" randomization

SystemVerilog
4

In reply to ajeetha:

I have one more solution for the same. In this, randomization does not repeat until all the possible states.

class one_hot;

rand bit[0:31] state;
randc bit[0:4] one_hot_bit;

constraint one_hot_state {
foreach (state[i])
if(i == one_hot_bit) state[31-i]==1;
else state[31-i]==0;
}

function void my_display();
$display(“Value of state is %b, value of one_hot_bit is %d\n”, state, one_hot_bit);
endfunction

endclass

class two_hot;

rand bit[0:31] state;
randc bit[0:4] first_hot_bit;
randc bit[0:4] second_hot_bit;

constraint two_hot {
first_hot_bit != second_hot_bit;
}

constraint one_hot_state {
foreach (state[i])
if(i == first_hot_bit) state[31-i]==1;
else if (i == second_hot_bit ) state[31-i]==1;
else state[31-i]==0;
}

function void my_display();
$display(“Value of state is %b, value of first_hot_bit is %d, value of second_hot_bit is %d\n”, state, first_hot_bit, second_hot_bit);
endfunction

endclass

program p1;
one_hot ONEHOT = new();
two_hot TWOHOT = new();

initial begin
repeat(32) begin
ONEHOT.randomize();
TWOHOT.randomize();
ONEHOT.my_display();
TWOHOT.my_display();
end
end

endprogram