Ho to pass a dynamic array to a constant function

SystemVerilog
,
2

In reply to noel:

You cannot declare a fixed sized array using a variable for its size. There is no reason the following should not be synthesizable except that synthesis tools do not allow dynamic arrays except as declared as a constant.

module top;
  function automatic int fmax
    (
      input int array_of_int []
    );
    int max_value = array_of_int[0];
    for(int i=0; i < $size(array_of_int); ++i)
      if (array_of_int[i] > max_value)
        max_value = array_of_int[i];
      return(max_value);
  endfunction
  parameter int A[] = {1,2,3,4};
  
  int B[3] = {3,2,1};
  logic [31:0] max;
  initial begin
    max = fmax(A);
    $display(max);
    max = fmax(B);
    $display(max);
  end
endmodule

However most synthesis tools accepts static methods of parameterized classes

module top;

  class C#(int size);
    static function int fmax
    (
      input int array_of_int [size]
    );
    int max_value = array_of_int[0];
      for(int i=0; i < size; ++i)
      if (array_of_int[i] > max_value)
        max_value = array_of_int[i];
      return(max_value);
  endfunction
  endclass
  parameter int A[] = {1,2,3,4};
  
  int B[3] = {3,2,1};
  
  logic [31:0] max;
  initial begin
    max = C#($size(A))::fmax(A);
    $display(max);
    max = C#($size(B))::fmax(B);
    $display(max);
  end
endmodule