Here in my code im trying to skip the print of a , when we do new for the first time. then onwards it should print a as im defining ABC. but its not picking the `define ABC. can we use `define in class?

SystemVerilog
1 
class cls;
  int a;

  `ifdef ABC
 initial begin
     a=10;
 end
  `endif
  
  function new();
    `ifdef ABC

    $display("a=%0d",a);

    `else

    $display("ABC not set");

    `endif
    
  `ifndef ABC

    `define ABC

  `endif
  endfunction
 
  
endclass

module m;
  initial begin
    repeat(2)begin
      cls c;
    c=new();
  end
  end
endmodule
2

`define is a pre-processor directive for the compiler, and will only affect the processing of code after the directive. The `ifdef/`ifndef statements in your code don’t recognize the `define ABC since the `define occurs after those statements.

3

I explicitly want to skip the print for the first time when i instantiate the class.
i want the print 2nd time when i instantiate the class.

4

Compiler directives like `ifdef and `define are not procedural code. They get processed as the compiler is scanning the text of your code, before understands any SystemVerilog constructs.

To get the behavior you want, you need to declare a static class variable. This is like a global variable, and not per instance of the class.

class cls;
  int a;
  static bit ABC;
  function new();
    if (ABC) begin
      a = 10;
      $display("a=%0d",a);
    end else begin
      $display("ABC not set");
      ABC = 1;
    end
  endfunction
endclass

module m;
  cls c;
  initial
    repeat(2)
      c=new();
endmodule
1 Like
5

understood.
thanks.
I too implemented similarly using static variables.