Help with assert for two different posedges

SystemVerilog
1

Hi
I would like to get some help-
My module receives reset from other domain. The reset is up only for one clock cycle of the reset’s clock domain. At posedge of my module’s clock it should sample the reset, and then at the next posedge the signal should be cleared.
I had a situations where my clock was slower than the reset’s clock, so it missed the reset sample.
I want to write an assertion for that situation.
My problem now is that the simulation evaluates the reset value at the end of the first posedge with it’s past value, and not with the next by value:

 initial begin
             forever @(posedge reset[idx]) begin
                 @(posedge clk);
                 assert (sig[idx] === 1'b0);
             end
         end

I don’t want to write another posedge… is the any way to make the simulation catch the next value?

thank you!

2

Your requirements are not clear.
If out module clock was slower than the reset’s clock, then sgouldn’t you latch the external reset first, and then clock that latched reset signal with your module clock?
A diagram would help.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

3

Even better would be a minimal compete reproducible example with stimulus showing when the assertion should pass and fail.

4

Basically, you are right. We found it in specific test, where the freqs of the both domains were taken to an extreme. It was after rtl freeze. The designer will fix it in the next project. Meanwhile I just want to write an assert that will let me know if the randomization caused again this situation.