In reply to mmistry@apm.com:
In reply to ben@SystemVerilog.us:
Actually, I want to cover IDLE[1:N0]=>{NON_SEQ=>SEQ[1:MAX]}[1:N1]=>IDLE[1:N2] kind of transition in the covergroup for AHB.
Thanks,
Munjal
You. Could use something like the following example that demonstrate how to use variables for Dynamic range delays.
property p;
int lv = max_delay;
req |-> (lv > 0, lv = lv - 1)[*0:$] ##1 ack;
endproperty
A: assert property(@(posedge clk)p);
Ben