Handling input to output delay in Monitor sampling

In reply to chr_sue:
Monitor code that is shared gets both inputs and make a prediction of the expected result
Without the queue the code would look something like this

task run_phase(uvm_phase phase);
      jb_txm=jelly_bean_transaction::type_id::create("jb_txm");
      fork
	 forever begin  
	    @(posedge jb_vi.clk)
	       jelly_bean_transaction jb_txmq = new;
               if(jb_vi.valid == 1)
	       jb_txmq.a = jb_vi.a;
 	       jb_txmq.b=jb_vi.b;
	       jb_txmq.c=jb_txmq.a +jb_txmq.b ;
               if(jb_vi.valid_out == 1)
               ref_mon_a_port_after.write(jb_txmq);		
	      end
	 end
endtask:run_phase

This does not give the correct results as my inputs when the valid_out=1 is different from the inputs when valid =1 . I need to compute sum when valid=1 but this output is delayed until valid_out =1 . Hence i am computing the sum and storing the results in queue and fetching the stored results only when valid_out =1 .Is there any better way of doing this