Handling input to output delay in Monitor sampling

In reply to uvmsd:

Hi,
I dont understand how to use two analysis ports. In my case I have to compute the output at a particular valid signal but send it to scoreboard after a delay of three clock cycles based another signal flag.
This is how i am currently implementing using the buffer approach but i am curious to know how to implement using two ports instead.


class normal_add_ref_monitor_after extends uvm_monitor;
`uvm_component_utils(normal_add_ref_monitor_after)
  jelly_bean_transaction jb_txm;
   jelly_bean_transaction jb_txm_q[$];
virtual simpleadder_if jb_vi;
uvm_analysis_port#(jelly_bean_transaction) ref_mon_a_port_after;

   function new(string name="normal_add_ref_monitor_after",uvm_component parent);
      super.new(name,parent);
   endfunction :new
   function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      void'(uvm_resource_db#(virtual simpleadder_if)::read_by_name(.scope("ifs"), .name("simpleadder_if"), .val(jb_vi)));
      ref_mon_a_port_after=new("ref_mon_a_port_after",this);
   endfunction:build_phase
   task run_phase(uvm_phase phase);
      jb_txm=jelly_bean_transaction::type_id::create("jb_txm");
      fork
	 forever begin  
	    @(posedge jb_vi.clk)
	    
	      if(jb_vi.valid == 1) begin
	       jelly_bean_transaction jb_txmq = new;
	       
	       jb_txmq.a = jb_vi.a;
 	       jb_txmq.b=jb_vi.b;
	       jb_txmq.c=jb_txmq.a +jb_txmq.b ;
		 // add_mon_ref_add_result();
		 jb_txm_q.push_back(jb_txmq);
		 $display("queue = %p",jb_txm_q);
		 
		 
	       
		 
	      end
	 end
	 forever begin  
	    @(posedge jb_vi.clk)  
	      if(jb_vi.valid_out == 1) begin
		 jelly_bean_transaction jb_txmq = jb_txm_q[0];
		 ref_mon_a_port_after.write(jb_txmq);
		 `uvm_info("input_pop",$sformatf("value: %0d", jb_txm_q.pop_front()),UVM_LOW);
		
	      end
	 end // forever begin
      join
endtask:run_phase
endclass:normal_add_ref_monitor_after