In reply to chr_sue:
Hi Chr_sue,
if i could get your help looking into this : adding uvm_callback
This is how I am doing it, added comments
class base_drv extends uvm_driver#(base_tr);
`uvm_component_utils(base_drv)
`uvm_register_cb(base_drv, dr_callback_abs) // *************** UVM Callback
...
virtual task run_phase (uvm_phase phase);
super.run_phase(phase);
tr = base_tr::type_id::create("tr");
forever begin
seq_item_port.get_next_item(tr);
`uvm_do_callbacks(base_drv, dr_callback_abs, dr_cb_t1()); // *************** UVM Callback
@(vif.cb) vif.in <= tr.in;
`uvm_do_callbacks(base_drv, dr_callback_abs, dr_cb_t2()); // *************** UVM Callback
seq_item_port.item_done();
end
endtask
endclass
class dr_callback_abs extends uvm_callback; // *************** UVM Callback abstract class
`uvm_object_utils(dr_callback_abs)
function new(string name = "dr_callback_abs");
super.new(name);
endfunction
virtual task dr_cb_t1;
endtask
virtual task dr_cb_t2;
endtask
endclass
class dr_callback extends dr_callback_abs; // *************** UVM Callbackimplementation class
`uvm_object_utils(dr_callback)
function new(string name = "dr_callback");
super.new(name);
endfunction
virtual task dr_cb_t1();//base_tr cb_t);
`uvm_info(get_type_name(),$sformatf(" YOU ARE Inside dr_cb_t1 method"), UVM_LOW);
endtask
virtual task dr_cb_t2();//base_tr cb_t);
`uvm_info(get_type_name(),$sformatf(" YOU ARE Inside dr_cb_t2 method"), UVM_LOW);
endtask
endclass
// test file
`include "seq_1.sv"
`include "dr_callback.sv" // *************** UVM Callback: included callback class file (which has callback abstract class and implementation class) in test file
class all_8_test extends base_test;
dr_callback cb; // *************** UVM Callback: create handle of implementation class
`uvm_component_utils(all_8_test)
function new(string name = "all_8_test", uvm_component parent = null);
super.new(name, parent);
set_type_override_by_type(base_test::get_type(), all_8_test::get_type());
set_type_override_by_type(base_seq::get_type(), seq_1::get_type());
cb = dr_callback::type_id::create("cb", this); // *************** UVM Callback: create callback object
uvm_callbacks#(base_drv, dr_callback_abs)::add(env.agent.dr, cb); // *************** UVM Callback: add callback to driver
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.phase_done.set_drain_time(this,3);
endtask
endclass
Here is the code link : UVM : In progress - EDA Playground
I think this is something to do where to include callback class file when compiling. I have checked syntax multiple time, don’t see anything wrong there.
Right now I have included callback class file name it in my extended test file
Thanks for your time.
Error-[SE] Syntax error
Following verilog source has syntax error :
Token ‘dr_callback_abs’ not recognized as a type. Please check
whether it is misspelled, not visible/valid in the current context, or not
properly imported/exported. This is occurring in a context where a variable
declaration, a statement, or a sequence expression is expected. Either the
declaration type is not known or this is incorrect syntax.
“base_drv.sv”, 25 (expanding macro): token is ‘=’
`uvm_do_callbacks(base_drv, dr_callback_abs, dr_cb_t1()); //
*************** UVM Callback
^
#0, uvm_do_obj_callbacks(T=base_drv, CB=dr_callback_abs, OBJ=this, METHOD=dr_cb_t1()) : “/apps/vcsmx/vcs/Q-2020.03-SP1-1//etc/uvm-1.2/src/macros/uvm_callback_defines.svh”:165
#1, uvm_do_callbacks(T=base_drv, CB=dr_callback_abs, METHOD=dr_cb_t1()) : “/apps/vcsmx/vcs/Q-2020.03-SP1-1//etc/uvm-1.2/src/macros/uvm_callback_defines.svh”:140
full expansion of macro (uvm_do_callbacks), error at line 3
(* native_uvm *)begin
uvm_callback_iter#(base_drv,dr_callback_abs) iter = new(this);
=> dr_callback_abs cb = iter.first();
while(cb != null) begin
`uvm_cb_trace_noobj(cb,$sformatf(“Executing callback method ‘dr_cb_t1()’ for callback %s (dr_callback_abs) from %s (base_drv)”,cb.get_name(), this.get_full_name()))
…