Get interface type from parameter

SystemVerilog
, ,
3

In reply to dave_59:

do you mean that you cannot parameterized interface with specific types? As far as I know, you can parameterize interfaces based on this example:

https://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/parameterized_interface/

They have an example that looks like :


interface clkndata_if #(parameter AW = 1, DW = 1);
  ...
  bit [AW-1:0] addr;
  bit [DW-1:0] data;
  // Other variables, wires, and parameters
...

I’ve seen code that looks like:


interface some_if #(parameter type some_struct_t = default_struct_t)
(
  input wire clk,
  input wire rst_n
)
...