Generating unique values without randc

SystemVerilog
, ,
2

In reply to Krishna9:


module top ;
  
  class rranc ;
    rand bit [15:0] val;
    int qval[$];
    
    constraint c_r{
      !(val inside {qval}) ;
    }
    
    function void post_randomize();
      if(qval.size >= 2**$bits(val)-1) 
        qval = {};
      qval.push_back(val);
    endfunction  
  endclass 
  
  initial begin 
    rranc r  = new ;
    repeat(32) begin 
      
      r.randomize();
      $display("%p",r);
      
    end 
    
  end
  
endmodule