Generate non repeating values in an array of class

SystemVerilog
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2

In reply to bachan21:

Your CYCLIC constraint only checks that adjacent elements are not the same. SystemVerilog has a unique constraint that does what you want:

class A;
  rand bit [3:0] value [10];
  constraint C1 { foreach(value[i]) value[i] inside {[1:10]}; }
  constraint CYCLIC { unique {value}; }
endclass:A
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