Generate coverages by loop and function

SystemVerilog
2

In reply to alexd555:

Your pseudo code does not match your comments, and you never specified what is is that you wanted to sample. Since you were having trouble with covertgroup syntax and explaining what kind of coverage you are looking for it would really help to shoe a complete example that manually calculate coverage without using a covergroup

module manual_coverage;
  bit my_bins[bit [2:0]];
  bit [2:0] sample;
  int sum_of_bins_hit;
  initial begin
    for(int i=0;i<3;i++) // this creates bins 3'b000, 3'b010, and 3'b110
      my_bins[i<<1] = 0;
    // generate random stimulus
    repeat(7) begin
      sample = $urandom;
      if(my_bins.exists(sample)) begin
        $display("sample value %b bin hit", sample);
        my_bins[sample] = 1;
      end 
      else
        $display("sample value %b does not hit a bin",sample);
    end
    sum_of_bins_hit = my_bins.sum() with (int'(item));
    $display("Final coverage is bins hit %d / Total bins %d", sum_of_bins_hit, my_bins.size());
    $display("%d%% Final coverage percentage", 100*sum_of_bins_hit/my_bins.size());
  end
endmodule