Functions in Constraints

SystemVerilog
4

In reply to prashantk:


constraint end_addr_c {
  (start_addr<0) -> (end_addr==0); // dummy rule, bit type is unsigned
  // (start_addr>=0) -> (end_addr!=0 && (end_addr==start_addr)); // wrong
  end_addr == (start_addr << 1);
};