Functional coverage : bins creation

Coverage
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1

Hi All,

“while defining a coverpoint, if user did not specify any bin, SV automatically creates a vector bin of size 64”.

case_1:

bit [1:0] addr; //2bit, so sampled values are 0 1 2 3
covergroup CG @(posedge clk);
L1 : coverpoint addr;
endgroup

Here 64 bins are created? If yes, only 4 bins will sample 4 possible values, how about remaining 60 bins?

case_2:

int unsigned addr;
covergroup CG @(posedge clk);
L1 : coverpoint addr;
endgroup

Here also 64 bins are created?

Could you please clarify, in both the cases how many bins are created?

Thank You,

2

In reply to Thirumalesh Kumar:

For case_1, the LRM says: 'If the number of bins exceeds the number of values, then some of the bins will be empty". Empty bins get excluded from the coverage calculation.

For case_2, the LRM says: “If a fixed number of bins is specified and that number is smaller than the specified number of values, then the bin values are uniformly distributed among the specified bins”. Then each bin covers 67108864 values.

See section 19.5.1 Specifying bins for values in the IEEE 1800-2017 SystemVerilog LRM.

3

Case 1: bit [1:0] , so by default 4 bins are created.
Case 2: int unsigned, so by default 64 bit vector bin.

The default bin is essentially a catch-all bin that ensures all sampled values are covered. The unused bits in the default bin are effectively ignored and do not represent additional bins. The purpose of the default bin is to capture any value that is not explicitly covered by other bins.