In reply to sanjeevs:
Your failing code is illegal according to the SystemVerilog 1800-2012 LRM. (see 6.21 Scope and lifetime). Your simulator should have generated an error.
You are not allowed to have an initialization on a variable whose lifetime is implicitly static and has the option to be declared automatic. This is because unlike most programming languages, the default lifetime of variables in a function is static, and initialization of static variables happens before time 0, not when calling the function. In your example, you are expecting i to behave as an automatic. So you need to do one of the following
- explicitly declare i automatic
- declare the function automatic, which makes variable declared inside it implicitly automatic
- declare the module automatic, which makes functions declared inside it implicitly automatic
- split the declaration and initialization so that the initialization happens when the function gets called.