Fork thread priority

SystemVerilog
1 

fork : my_fork
    begin
        @(negedge clka);
        ... // this shouldn't be executed if negedge clka and negedge clkb happens at the same time.
    end
    begin
        @(negedge clkb);
        disable my_fork;  // I want this to execute first if negedge clka and negedge clkb happens at the same time.
    end
join_any

So I want to make sure that if clka and clkb go from 1 to 0 at the same simulation time unit, the disable my_fork should be prioritized. How can I achieve that?

2

In reply to kjhhgt76:

In the general case, there is no way to know if two clock transitioned in the same time unit until after that time unit is over.

If we know the transitions occur in the same event region, then we can know they transition in the next event region of the same time unit. It would help to know how there clocks are generated and if there is another common reference clock between them.

It would also help to know what do you plan to do in these two threads as moving them to another event region might cause other issues.

3

In reply to dave_59:

I am writing a monitor for i2c protocol which needs to distinguish between repeated start and the data writing to slave during the high stage of sclk. So I try to use a fork to do that.


i2c_write = 1;
fork : my_fork
    begin
        @(negedge sda);
        i2c_write = 0;
        disable my_fork;
    end
    begin
        @(negedge sclk);
        disable my_fork;
    end
join_any

When both of them turn from 1 to 0 at the same time, it should be treated as i2c write. The first fork shouldn’t be executed if that happens.