In reply to mikefitzgerald:
The problem is the Test is the least reusable component of your testbench, and there is no generic way of knowing when the test is done. A decent general solution for launching threads and ending a basic OO SystemVerilog testbench is using the UVM. (Sorry, you set yourself up for that!)
The UVM objection mechanism simplifies this by giving any component the ability to raise an objection to ending the test. The test ends when there are no more objections. It act like a semaphore in reverse.