In reply to dave_59:
Thanks, but from a practical standpoint, it seems like the software would be ‘cleaner’ and more structured if we keep functions clean and avoid calling tasks from within.
From the very beginning of the development of rtl languages, we at Hughes picked VHDL because it is more structured and has rules to avoid funny stuff. Verilog is so flexible that it is easy to create weird code and get oneself into TROUBLE. Systemverilog inherited some of these quirks.
However, if one adopts good discipline in the use of the language then we can avoid a lot of problems.
Ben