Forcing values of bind ports through concatenated signals on inner instance port connection

SystemVerilog
,
1

Hello,

I am trying to force values on a module’s output ports (pretty standard procedure) and encountering some odd behavior (simulator is VCS). I have the following setup:


module unit (
    output a,
    output b
);


...

module unit_bind (
     output a,
    output b
)


drv_data #(.PORT_NUM(2)) drv_outputs(
.clk(clk), 
.data(`TEST_DATA), 
.out_port({a, b}));
...

drv_data #(
    parameter PORT_NUM = 0
)(
    input clk,
    input [SENT_CONN_PACKET_SIZE-1:0] data [PORT_NUM], 
    output out_port [PORT_NUM]
);

    reg temp [PORT_NUM];
    int count, i;

    initial 
        $deposit(count,0);
    
    always @(negedge test_pkg::clk) begin
        for (i=0; i< PORT_NUM; i++) begin
            temp[i] = data[i][(SENT_CONN_PACKET_SIZE-1-count)];
        end 
        force out_port[PORT_NUM-1:0] = temp[PORT_NUM-1:0];
        if (count < SENT_CONN_PACKET_SIZE) begin
            count = count + 1;  
        end
    end
    
endmodule

...

 bind unit unit_bind bind_inst (.*);

Inside the drv_data instance, I see the correct values on “out_port”. However, the external ports (in the bind) are unaffected.

Would appreciate any help since I am not sure what I’m missing.

2

image
image703×63 7.51 KB

The first signal is the out_ports port, whereas the two rows of Xs below it are the bound module’s ports. Furthermore, if I only connect a single signal in the drv_data instance:

drv_data #(.PORT_NUM(1)) drv_outputs(
.clk(clk),
.data(`TEST_DATA),
.out_port(a));

Then the force statement works as expected.

3

It would be helpful if you provided a complete example which can be compiled and executed, preferably on EDA Playground. It is difficult to discern what you are trying to accomplish with the snippets of code that you provided.

4

@cgales My apologies. I threw together an example here, apologies if it is slightly spaghetti-like:

You can see that the module port is constantly at 0, while the inner value is forced. The force does not propagate through the port, which is my issue.

5

First thing you should do is closely look at the warnings you are getting, or run with a different simulator. You have several errors which should prevent your code from compiling, but your simulator of choice doesn’t report them as errors.

Also, I don’t see any bind() statement in the code you posted.

6

@cgales My apologies, that was very unprofessional. I fixed the warnings and added the obviously missing bind statement.

7

Your updated code still generates errors in three of the four commercial simulators on EDA Playground. You should analyze these errors and fix your code.