In reply to robert.liu:
The correct answer is src = 5.
As I mentioned from section 23.3.3.1 Port coercion results in all ports with connections to nets on both sides being treated as collapsed. The text in 3.9.6 Port connections is basically saying the same thing, although this text was straight from Verilog before SystemVerilog added the capability to add variables to input port declarations and output port instance connections.