Force inout port

SystemVerilog
5

In reply to dave_59:

Thanks Dave. I studied more in the direction of “port collapsing” and finally understand why force statement in my small test case worked that way.

I have another related question below, on port connection and its implicit continuous assignment and the unidirectional property of continuous assignment.

module test;
wire integer foo;
assign foo = 3;
dut dut(foo);
endmodule

module dut(input integer bar);
initial #2 force bar = 5;
initial begin
    #10;
    $display("dst = ", bar,,,"src = ", test.foo);
    $finish;
end
endmodule

hi-conn signal of input port bar is a wire and input port is a variable, I assume there is an implicit continuous assignment here like

assign test.dut.bar = test.foo;

The simulation results on multiple simulator kind of surprised me since one output src = 3 while another output src = 5. Which one is correct?